In a known bus arbitration scheme, at one system clock cycle the bus requests which are current are loaded into a register, and at the next system clock cycle the requests held in the register are arbitrated by a state machine to determine which request to grant. The register is necessary to overcome metastability problems; without the register if a request were to change at the time of arbitration, an incorrect grant, or "glitch" is likely to arise.
A problem with the arbitration system described above concerns the speed of arbitration. If a request is made immediately after a clock cycle begins, it will not be loaded into the register until just under one clock cycle later, and it will not be arbitrated until the next clock cycle. Thus, if the system clock has a frequency of 50 MHz, it can take up to 40 ns before a request is arbitrated. There is a desire to shorten the arbitration period to 20 ns, or less. However, increasing the system clock frequency above 50 MHz, for example to 100 MHz, presents practical problems with present technology.